High Performance Reconfigurable Processing

• Country: Netherlands
• Summary: High Performance Reconfigurable Processing
• NLT Ref No: 102554792
• Deadline: 23 Jul 2024
• Financier: Other Funding Agencies
• Purchaser Ownership: Government
• Tender Value: Refer Document
• Notice Type: Tender
• Document Ref. No.: 1-12151
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• Description:
• Tenders are invited for High Performance Reconfigurable Processing Price Range 500 KEURO The activity aims at providing a high performance and flexible solution for payload data processing tasks using EEE parts which are designed for space applications.The approach while designing a High Performance Reconfigurable Processing Module will follow the general principles organized with the following tasks:- Implementing real-time data stream processing functions in FPGA firmware.- Implementing non-real time and lower data rate processing in software.- Providing a scalable and versatile I/O system supported by flexible software drivers.- Extending digital I/Os by Analogue Front-ends.- Developing at EBB level a HW module hosting a high endprocessor or DSP, high performance and capacity FPGAs, a Space Fibre router to interlink the processing nodes and corresponding support equipment.- Implementing and validating on the target with a selection of IP Cores taken from ESA's portfolio.The selected hardware platform is the combination of a powerful processor or DSP, one or several high-end reconfigurable FPGAs and a Space Fibre network interlinking the processing nodes, based on EEEparts which are designed for space applications. The platform shall fulfil the following needs:- Supporting exploratory and evolutionary designs according to mission needs during early development phases. The advantage at this stage is clearly to reduce costs thanks to using a flight representative and stable hardware platform.- Allowing in-flight reconfiguration for adaptation and to allow for algorithm changes during mission lifetime, different mission phases and modes. For instance, processing algorithms can be tuned according to evolving needs or re-defined during the execution of the mission. This will extend the level of data processing to be applied on board, as acceptance of the sciencecommunity will be higher in this case than fixing the processing chain before the launch for the whole mission lifetime.- Allowing in-flight partial reconfiguration to prepare theprocessing chain for the next task without service interruption of the on-going task.- Allowing staggered data processing by using in-flightreconfiguration of the processing chain. This will tremendously reduce the number of processing nodes, if the application allows for staggered processing, as the same processing chain can be used for different tasks.- Using the same processing chain for different instruments by using in-flight reconfiguration. This is possible when several instruments work in windowing mode and do not need the processing chain all the time.- Enabling a mission rescue in case of FDIR events or failures that could be overcome by a deep reconfiguration of the data processing functions.The activity will consist in developing at EBB level a HW module hosting a high end processor or DSP, high performance and capacity FPGAs, a Space Fibre router to interlink the processing nodes and corresponding support equipment. A selection of IP Cores taken from ESA's portfolio will be implemented and validated on the target.Read more
• Documents:

 Tender Notice